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Design & Test of Computers
Special Issue on Design and Test for Building Ultra High-Speed Networks

http://www.computer.org/dt/

CALL FOR PAPERS

Scope -- Submission and Review Procedures

Scope

Rapid advancements in optical and wireless networking technologies have so increased the capacity of physical links that considerable bandwidth is now available. This trend, along with the ever-increasing demand for advanced functionality and sophisticated services, significantly augments the workload of hardware networking components such as ASICs, SoCs, NoCs, SiPs, boards, and multiboard systems. There are new design, manufacturing, and test challenges for these highly heterogeneous, complex, mixed-signal devices. These challenges will grow as the available bandwidth of the physical links increases even more quickly than the speed of manufactured silicon devices. Designers adopt emerging digital and mixed-signal silicon manufacturing technologies in such components to keep pace with physical media speed, adding new yield and manufacturability problems related to their testability. Addressing these problems requires advanced modeling, design, verification, debugging, and testing methodologies. All these methodologies and corresponding tools are critical for the efficient implementation and unhindered production of future, ultra high-speed, wired and wireless network systems.

IEEE Design & Test seeks original manuscripts for a special issue on Design and Test for Building Ultra High-Speed Networks, scheduled for publication in July-August 2007. The goal of this special issue is to present a consolidated study of the state of the art and identify primary research and development directions in the design, test, and evaluation of hardware components for ultra high-speed networks, including design and test methods and tools, implementation practices, and evaluation experiments. Tutorials and surveys are also welcome. Topics of interest include

  • Design and test methodologies, practices, and tools for wired and wireless networking components
  • Performance analysis flows, tools, and benchmarks for hardware components of networking systems
  • Energy- and power-aware design and test of network components
  • System-level design, test, and simulation flows for networking systems
Submission and Review Procedures
top

Prospective authors should follow the submission guidelines for IEEE Design & Test. All manuscripts must be submitted electronically to the IEEE Manuscript Central Web site at http://cs-ieee.manuscriptcentral.com. Indicate that you are submitting your article to the special issue on "Design and Test for Building Ultra High-Speed Networks." All papers will undergo the standard IEEE Design & Test review process. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere. Accepted articles will be edited for structure, style, clarity, and readability. Please see IEEE D&T Author Resources at http://www.computer.org/dt/author.htm, and then scroll down and click on Author Center for submission guidelines and requirements.

Schedule

Submission Deadline: January 3, 2007
Reviews Completed: March 5, 2007
Revisions Due (if necessary): March 25, 2007
Notification of Final Acceptance: April 6, 2007
Submission of Final Version: April 20, 2007

Guest Editors:

Ioannis Papaefstathiou
Technical University of Crete
ygp@mhl.tuc.gr
Nikos Nikolaou
EFG e-Solutions
nikolaou@telecom.ntua.gr
David Greaves
University of Cam
djg@cl.cam.ac.uk
Maria Gabrani
IBM Research Zurich

mga@zurich.ibm.com
Dimitris Gizopoulos
University of Piraeus
dgizop@unipi.gr

IEEE Computer Society – Test Technology Technical Council

TTTC CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

SENIOR PAST CHAIR
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


TTTC 2ND VICE CHAIR
Joan FIGUERAS
Universitat Politècnica de Catalunya - Spain
Tel. +34-93-401-6603
E-mail figueras@eel.upc.es

FINANCE
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

DESIGN & TEST MAGAZINE
Tim CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG

Lucent Technologies
- USA
Tel. +1-732-949-5539
E-mail chenhuan@lucent.com

TECHNICAL ACTIVITIES
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

ASIA & SOUTH PACIFIC
Hideo FUJIWARA
Nara Institute of Science and Technology - Japan
Tel. +81-74-372-5220
E-mail fujiwara@is.aist-nara.ac.jp

LATIN AMERICA
Marcelo LUBASZEWSKI
Federal University of Rio Grande do Sul - Brazil
Tel. +34-93-401-6603
E-mail luba@vortex.ufrgs.br

NORTH AMERICA
William R. MANN
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

 

PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 1ST VICE CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

INTERNATIONAL TEST CONFERENCE
Scott DAVIDSON
Sun Microsystems
- USA
Tel. +1-650-786-7256
E-mail scott.davidson@eng.sun.com

TEST WEEK COORDINATION
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
- USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
Michael NICOLAIDIS
iRoC Technologies - France
Tel. +33-4-381-20763
E-mail michael.nicolaidis@iroctech.com

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it


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